Field
The disclosure relates generally to a voltage regulator and, more particularly, to a low dropout regulator thereof.
Description of the Related Art
Low dropout (LDO) regulators are commonly used to regulate internal voltage supplies at lower voltage from higher voltages. Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The control of the regulated voltage over variations in both semiconductor processes and temperature is key to many applications. Additionally, power consumption is also a key design requirement.
FIG. 1 is a circuit schematic of a prior art low dropout (LDO) regulator with separate bandgap network. FIG. 1 consists of three stages. The first stage, stage 1, establishes the voltage reference. The second stage, stage 2, is the voltage regulator that uses this reference to make a regulated rail, VREG. The third stage, stage 3, is the Power-On-Reset, which measures the regulated voltage, VREG and generates a rising edge on its output port when the regulated voltage VREG exceeds a given percentage of its intended regulated value. It is desirable to merge the reference voltage, VREF, and regulated voltage generator, VREG, by directly creating a voltage that is temperature compensated.
FIG. 1 shows the circuit power supply voltage VDD 10, and ground VSS 20. The network can be understood as three stages. The first stage provides a voltage reference, VREF, as its output. The second stage consists of an operational amplifier, and a feedback loop which serves as a control of the regulator output transistor. The third stage establishes the regulated voltage, VREG, with a pass transistor, and a load. In the third stage, the output voltage of the network is VOUT 30 which is also the regulated voltage VREG. The first operational amplifier OA1 40 produces a reference voltage VREF and is electrically connected to a second operational amplifier OA2 50. The second operational amplifier OA2 50 is electrically coupled to the PFET output device 60. The PFET 60 is electrically coupled to the output VOUT 30 and load element 55. The operational amplifier OA2 50 has a first input 51 and second input 52. The OA2 input signal 52 is connected to a resistor feedback network formed from resistor RLH 53, and resistor RLL 54. In the first stage, a resistor RF 70 and resistor RF 75 are electrically coupled to the first and second input of operational amplifier OA1 40. Additionally, resistor RF 70 and RF 75 are coupled to the npn transistors NPN1, and NPN2, respectively. The npn transistor NPN1 80 is coupled to resistor element RPTAT 90. The npn transistor NPN2 85 is coupled to resistor element RA 95.
FIG. 2 is a circuit schematic of a network that provides an R-SHIFT method. FIG. 2 shows a prior art bandgap circuit schematic. From the FIG. 2 circuit schematic, an R-SHIFT method is described. In the circuit 200, the voltage supply VDD 210 supports the network, with a ground VSS 220. The output voltage is the regulated voltage VREG 230 at the output voltage. The operational amplifier OA1 240 provides an output signal to the gate of the PMOS pass transistor 260. A first resistor RF1 270 and second resistor RF2 275 are electrically coupled to the operational amplifier OA1 240. Additionally, there are a first and second device represented as a first diode 280 of size 1, and a second diode 285 of size N. The resistor RPTAT 290 is coupled to the diode 285, RSHIFT resistor 250, and operational amplifier OA1 240.
A shift resistance RSHIFT increases the current through the resistances RF and shifts up from 1.2V to an arbitrarily value VREG. By setting properly RF, RSHIFT, RPTAT and N, VREG is directly compensated in temperature, but this comes at the cost of two very large resistors RF and an operational amplifier.
FIG. 3 illustrates a circuit schematic 300 that highlights the R-String method. In FIG. 3, the bandgap cell is indirectly regulated to 1.25 V through a resistor ladder network. The ground potential VSS is 320, and the output rail VOUT 310 is established by the resistor ladder network, and operational amplifier OA1 340. The regulated voltage node 330 is electrically coupled to the resistor ladder network resistor R3 350 and resistor R4 355. The inputs of the operational amplifier OA1 340 are coupled to resistor RF1 370 and resistor RF2 375. The npn transistors 380 and 385 are coupled to the OA1 input signals. Resistor R1 390 (PTAT resistor), and resistor R2 395 are coupled to the npn transistor 380 and 385.
The output voltage, VOUT, VOUT=VREG is adjusted by the operational amplifier OA1 340 such that its fraction R4/(R3+R4) matches ˜1.25V. Then it is possible to optimize only the left part (bandgap part) to compensate it in temperature, and so the same compensation will also result for VOUT=VREG.
FIG. 4 illustrates an additional circuit schematic 400. In the prior implementation of FIG. 3 there is a resistive path between VREG and ground VSS. This will require large resistor values which is not desirable. FIG. 4 is a circuit schematic 400 that utilizes a power supply voltage VDD 410 and ground potential 420. The npn transistor pair NPN1 480 (size N) and NPN2 485 (size 1) are coupled to resistor RPTAT 490 and resistor RS 495. The base of the npn transistors establishes the reference voltage VREF and is electrically connected to resistor RH 453, and resistor RL 454. The npn transistors are sourced by a current mirror formed by PFET 430A and PFET 430B. The current mirror PFET 430A is connected to the gate of the PFET MPLOOP 425. A second PFET current mirror is electrically coupled to the power supply voltage VDD 410 formed by PFET mirror 435A and 435B. The transistor MPLOOP 425 is coupled to an NFET current mirror 445A and 445B.
The disadvantage of this circuit topology is the sensitivity to the regulated voltage VREG. If the regulated voltage, VREG, has noise, it is amplified because the voltage is applied on the gate-to-source voltage of the MPLOOP.
FIG. 5 shows a circuit schematic of an indirect PTAT 500. The power supply VDD 510 and the ground reference VSS 520 supply circuit 500. The network has a PFET current mirror M1 530A and M3 530B. The output pass transistor is a PFET (e.g. PMOS) M4 540. The PFET current mirror maintains a controlled current through the NPN Q1 535 and NPN current mirror formed by Q2 545A and Q3 545B. The base of NPN Q1 is coupled to resistor R1 560, resistor R2 570, and resistor R3 580, as well as NPN Q4 550.
The PTAT effect is done by matching the current in Q2 545A (N elements) with the current in Q1 535 (1 element) through the VREG loop. VREG is adjusted for this matching and {R2 570, R3 580} allow adjusting the value of VREG. This implementation has the following disadvantages and drawbacks:                The loop gain is low, which leads to any fluctuation on VREG becoming a current (VREG-VBE4)/R2, which is then copied with a low ratio to Q1. Only the line VCTL offers the gain.        The PSRR is poor because VCTL is supplied as a reference voltage. Noise on the power supply node, VDD, is applied on VGSM4 and the loop needs to be very fast to compensate for this noise.        Mostly, it is not high-voltage compliant. For example, if the power supply voltage, VDD, is VDD=20V, then the gate of PMOS transistor M1 530A is 19V and npn Q1 535 will undergo electrical breakdown for a standard 5V process. If transistors are stacked, in a series cascode configuration, the series cascode can protect its collector; this leads to a non-starting loop because the cascades themselves need to be started, otherwise they are blocking the regulation path. The issue of high voltage compliance is also true for the transistor Q3 545B.        Addressing the issue with series cascode transistors is achievable, but with an impact on the minimum voltage of operation (e.g. series cascode configuration leads to multiple drain-to-source voltage drops (VDSsat).        
U.S. Pat. No. 6,995,587 to Xi, describes a method for generating a bandgap reference current. The method for generating a bandgap reference current includes the steps for mirroring the bandgap reference current, summing the mirrored currents, and modulating and outputting a bandgap reference voltage from the sum. Representative preferred embodiments are disclosed in which the methods of the invention are used in providing under-voltage protection and in providing a regulated output voltage. Preferred embodiments of the invention include a bandgap under-voltage detection circuit using a comparator and a voltage regulator circuit having a regulated voltage output capability.
U.S. Pat. No. 6,512,398 to Sonoyama describes a circuit device with improved reliability by minimizing the fluctuations of the detection level of the supply voltage. The circuit device comprises a differential amplifier circuit that amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section and the detection voltage obtained by dividing a supply voltage. The reference voltage generating section generates reference voltage VREF from the base-emitter voltage of a bipolar transistor.
A bandgap voltage reference is discussed in the Analog Devices data sheet for AD580. The AD580 Data Sheet discloses a 3-terminal, low cost, temperature-compensated, bandgap voltage reference, which provides a fixed 2.5V output for inputs between 4.5V and 30V. A unique combination of advanced circuit design and thin film resistors provide the AD580 with an initial tolerance of ±0.4%, a temperature stability of better than 10 ppm/° C., and long-term stability of better than 250 pV.
In these prior art embodiments, the solution to establish an efficient voltage regulator utilized various alternative solutions.